1. Field of the Invention
The present invention relates to a method for manufacturing a lamination type semiconductor integrated device, in particular to a method for manufacturing a lamination type semiconductor integrated device in a wafer level using a TSV (Through Silicon Via) technology.
2. Description of the Related Art
A semiconductor integrated device is used in large quantity for industrial goods and so on. However, due to increasing speed of a device and miniaturization of a mounting device, further minuter packaging area, higher integration, and further reduction of wiring resistance in view of distance reduction among wirings is required.
In order to realize further minuter packaging area, higher integration, and distance reduction among wirings, an investigation is being carried out to integrate a plurality of packages into one package in a semiconductor integrated device and the result has been practically used.
In the past, after chopped into individual chips, they were packaged by an epoxy resin or the like; in this way a semiconductor integrated device has been provided. In recent years, because of reduction of packaging area and increase of operation speed, such methods as a PoP (Package on Package) which involves further packaging of packaged semiconductor integrated devices and a W/B method which involves bonding of chipped semiconductor integrated devices by wire bonding as they are in the chip form have been developed.
In recent years, to further increase action speed, miniaturize, reduce packaging area, and reduce wiring resistance, a so-called lamination type semiconductor integrated device formed of a lamination of a semiconductor integrated device with a different semiconductor integrated device, not by using wire bonding, has been developed. Currently, a lamination type semiconductor integrated device is being made by a method in which semiconductor integrated devices chopped into individual chips are laminated (Chip-on-Chip, or CoC) or a method in which individually chopped semiconductor integrated devices are laminated while keeping the form of a semiconductor wafer only in the lowest layer (Chip-on-Wafer, or Cola).
CoC and CoW have a high possibility of producing a product without defect, because a semiconductor integrated device chip without defect can be selected individually and a lamination type semiconductor integrated device is produced after laminating these chips without defect; on the other hand, CoC and CoW have such problems that: position accuracy at the time of laminating is necessary in each of semiconductor integrated devices because of miniaturization of the chip size and mass production is difficult because each chip is laminated sequentially.
In view of the above-mentioned, as a method for manufacturing laminated semiconductor integrated device in lower cost and larger quantity, it has been proposed a lamination type semiconductor integrated device wherein each semiconductor integrated device formed on a semiconductor wafer are laminated all at once by electrical bonding in the state of a semiconductor wafer without chopping. This semiconductor integrated device has a merit that the semiconductor integrated devices are bonded electrically in the vertical direction thereby enabling to reduce wiring resistance and packaging area, in addition, it can easily realize position accuracy and laminating can be done all at once.
One example of the production method is that after a semiconductor integrated device is formed on a semiconductor wafer, another support substrate for processing is bonded on surface of the semiconductor integrated device and then the semiconductor wafer is made thin by back side grinding, etching, and the like. Then, after a deep through hole having large aspect ratio is formed by using a technology such as anisotropic dry etching (a TSV technology: Trough Silicon Via technology), an insulator film is made in the through hole, which is then buried with an electric conductive material such as copper by plating or the like. The back of this semiconductor wafer is bonded by electrical bonding with surface of semiconductor wafer formed with another semiconductor integrated device, and then the support substrate for processing is debonded. These steps are executed sequentially thereby obtaining a lamination type semiconductor integrated device having a plurality of lamination layers of the semiconductor integrated device in the state of semiconductor wafer, that is, a Wafer-on-Wafer (WoW) method is exemplified.
In the foregoing method, a pressure-sensitive adhesive used to bond a support substrate for processing with surface of a semiconductor wafer having a formed semiconductor integrated device is required to simultaneously have, from grinding of the semiconductor wafer to debonding of the support substrate for processing after electrically bonding two semiconductor wafers arranged one above the other, grinding force resistance during back side grinding, small grinding striation, heat resistance in anisotropic dry etching during formation of a through hole, chemical resistance during plating and wet etching to remove grinding striation and to form a through hole, smooth debonding of the support substrate for processing at the end, low adherend staining, and the like.
To bond a support substrate for processing, a pressure-sensitive acryl adhesive or rubber adhesive has been used in the past. However, these adhesives are weak to heat, thereby leading to cause a problem that they are melted during heating process in the step of laminating by electrical bonding as mentioned above.
Alternatively, in the Japanese Patent Publication Number 3740451, a protection film for a semiconductor surface is proposed; this considers a thinning process such as back side grinding and etching, but does not mention at all about a behavior under heating condition especially such as exposing to 150° C. or higher for one hour or longer.
As mentioned above, there have been no methods for manufacturing a lamination type semiconductor integrated device that can simultaneously satisfy grinding force resistance during back side grinding of a semiconductor wafer, heat resistance during anisotropic dry etching and the like, chemical resistance during plating and etching, smooth debonding of a support substrate for processing at the end, and low adherend staining; and thus a lamination type semiconductor integrated device so far having been put to practical use by using a TSV technology is only in a mounting image sensor, which does not require debonding of a glass substrate, a support substrate for processing, at the end.